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in 1 in 2 d 1 d 2 s 1 s 2 v v+ gnd v l s 4 s 3 d 4 d 3 in 4 in 3 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 top view DG211B dual-in-line, soic and tssop DG211B/212b vishay siliconix document number: 70040 s-00788erev. h, 24-apr-00 www.vishay.com faxback 408-970-5600 4-1 improved quad cmos analog switches

22-v supply voltage rating ttl and cmos compatible logic low on-resistanceer ds(on) : 50 low leakageei d(on) : 20 pa single supply operation possible extended temperature range fast switchinget on : 120 ns low charge injectioneq: 1 pc wide analog signal range simple logic interface higher accuracy minimum transients reduced power consumption superior to dg211/212 space savings (tssop) industrial instrumentation test equipment communications systems disk drives computer peripherals portable instruments sample-and-hold circuits

the DG211B/212b analog switches are highly improved versions of the industry-standard dg211/212. these devices are fabricated in vishay siliconix' proprietary silicon gate cmos process, resulting in lower on-resistance, lower leakage, higher speed, and lower power consumption. these quad single-pole single-throw switches are designed for a wide variety of applications in t elecommunications, instrumentation, process control, c omputer peripherals, etc. an improved charge injection compensation design minimizes switching transients. the DG211B and dg212b can handle up to 22 v, and have an improved continuous current rating of 30 ma. an epitaxial layer prevents latchup. all devices feature true bi-directional performance in the on condition, and will block signals to the supply levels in the off condition. the DG211B is a normally closed switch and the dg212b is a normally open switch. (see truth table.)

logic DG211B dg212b 0 on off 1 off on logic a0o 0.8 v logic a1o 2.4 v
DG211B/212b vishay siliconix www.vishay.com faxback 408-970-5600 4-2 document number: 70040 s-00788erev. h, 24-apr-00
temp range package part number 40 85 c 16 - pin plastic dip DG211Bdj 40 85 c 16 - pin plastic dip dg212bdj 40 to 85 c 16 - pin narrow soic DG211Bdy 40 to 85 c 16 - pin narrow soic dg212bdy 16 - pin tssop DG211Bdq 16 - pin tssop dg212bdq
voltages referenced to v v+ 44 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd 25 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . digital inputs a v s , v d (v) 2 v to (v+) +2 v . . . . . . . . . . . . . . . . . . . . . . . . . . or 30 ma, whichever occurs first current, any terminal 30 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . peak current, s or d (pulsed at 1 ms, 10% duty cycle max) 100 ma . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature 65 to 125 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . power dissipation (package)b 16-pin plastic dip c 470 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-pin narrow soic and tssop d 640 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . notes: a. signals on s x , d x , or in x exceeding v+ or v will be clamped by internal diodes. limit forward diode current to maximum current ratings. b. all leads welded or soldered to pc board. c. derate 6.5 mw/ c above 75 c d. derate 7.6 mw/ c above 75 c
figure 1. d x s x v+ in x v level shift/ gnd v+ v drive v l
DG211B/212b vishay siliconix document number: 70040 s-00788erev. h, 24-apr-00 www.vishay.com faxback 408-970-5600 4-3
test conditions unless otherwise specified d suffix 40 to 85 c parameter symbol v+ = 15 v, v = 15 v v l = 5 v, v in = 2.4 v, 0.8 v e temp a min b typ c max b unit analog switch analog signal range d v analog full 15 15 v drain-source on-resistance r ds(on) v d = 10 v, i s = 1 ma room full 45 85 r ds(on) match r ds(on) d , s room 2 source off leakage current i s(off) v s = 14 v, v d = 14 v room full 0.5 5 0.01 0.5 5 a drain off leakage current i d(off) v d = 14 v, v s = 14 v room full 0.5 5 0.01 0.5 5 na drain on leakage current i d(on) v s = v d = 14 v room full 0.5 10 0.02 0.5 10 digital control input voltage high v inh full 2.4 v input voltage low v inl full 0.8 v input current i inh or i inl v inh or v inl full 1 1 a input capacitance c in room 5 pf dynamic characteristics turn-on time t on v s =10 v sfi 2 room 300 ns turn-off time t off s see figure 2 room 200 ns charge injection q c l = 1000 pf, v g = 0 v, r g = 0 room 1 pc source-off capacitance c s(off) v s = 0 v , f = 1 mhz room 5 f drain-off capacitance c d(off) v s = 0 v , f = 1 mhz room 5 pf channel on capacitance c d(on) v d = v s = 0 v, f = 1 mhz room 16 off isolation oirr c l = 15 pf, r l = 50 v 1 v f 100 kh room 90 db channel-to-channel crosstalk x talk l p, l v s = 1 v rms , f = 100 khz room 95 db power supply positive supply current i+ v in = 0 or 5 v room full 10 50 a negative supply current i v in = 0 or 5 v room full 10 50 a logic supply current i l room full 10 50 power supply range for continuous operation v op full 4.5 22 v
DG211B/212b vishay siliconix www.vishay.com faxback 408-970-5600 4-4 document number: 70040 s-00788erev. h, 24-apr-00

test conditions unless otherwise specified d suffix 40 to 85 c parameter symbol v+ = 12 v, v = 0 v v l = 5 v, v in = 2.4 v, 0.8 v e temp a min b typ c max b unit analog switch analog signal range d v analog full 0 12 v drain-source on-resistance r ds(on) v d = 3 v, 8 v, i s = 1 ma room full 90 160 200 dynamic characteristics turn-on time t on v s = 8 v sfi 2 room 300 ns turn-off time t off s see figure 2 room 200 ns charge injection q c l = 1 nf, v gen = 6 v, r gen = 0 room 4 pc power supply positive supply current i+ v in = 0 or 5 v room full 10 50 a negative supply current i v in = 0 or 5 v room full 10 50 a logic supply current i l room full 10 50 power supply range for continuous operation v op full 4.5 25 v notes: a. room = 25 c, full = as determined by the operating temperature suffix. b. the algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. c. typical values are for design aid only, not guaranteed nor subject to production testing. d. guaranteed by design, not subject to production test. e. v in = input voltage to perform proper function. 85 c 20 16 12 8 4 0 4 8 12 16 20 40 50 60 70 80 90 100 110 0 10 20 30 40 50 15 10 5 0 5 10 15 5 v r ds(on) vs. v d and power supply voltages v d drain voltage (v) 10 v 15 v 20 v r ds(on) vs. v d and temperature v d drain voltage (v) 125 c 25 c 55 c v+ = 15 v v = 15 v 30 20 10 60 70 80 90 100 r ds(on) drain-source on-resistance ( ) r ds(on) drain-source on-resistance ( )
DG211B/212b vishay siliconix document number: 70040 s-00788erev. h, 24-apr-00 www.vishay.com faxback 408-970-5600 4-5
0246810121416 0 25 50 75 100 125 150 175 200 225 r ds(on) vs. v d and single power supply voltages v d drain voltage (v) v+ = 5 v 7 v 10 v 12 v 15 v 250 20 15 10 5 0 5 10 15 20 40 20 0 20 40 leakage currents vs. analog voltage i s, i d current (pa) i s(off) , i d(off) i d(on) 55 25 45 5 15 65 1 na 100 pa 10 pa 35 1 pa 85 105 125 v+ = 15 v v = 15 v v s, v d = 14 v i s(off) , i d(off) i s, i d current temperature ( c) leakage current vs. temperature r ds(on) drain-source on-resistance ( ) v analog analog voltage (v) v+ = 22 v v = 22 v t a = 25 c 30 10 10 30 15 10 5 0 5 10 15 30 20 10 0 10 20 30 v+ = 15 v v = 15 v v+ = 12 v v = 0 v q charge (pc) q s, q d charge injection vs. analog voltage v analog analog voltage (v) oirr (db) 10 k 100 k 1 m 10 m 40 50 60 70 80 90 100 110 120 f frequency (hz) off isolation vs. frequency v+ = +15 v v = 15 v r l = 50
DG211B/212b vishay siliconix www.vishay.com faxback 408-970-5600 4-6 document number: 70040 s-00788erev. h, 24-apr-00 figure 2. switching time 50% 0 v 3 v t off t on v o t r <20 ns t f <20 ns logic input switch output 90% c l 35 pf r l 1 k v o = v s r l + r ds(on) r l v s = +2 v v o v v+ in s d 3 v 15 v gnd +15 v figure 3. off isolation s in r l d r g = 50 v s v o 0v, 2.4 v off isolation = 20 log v s v o v+ 15 v gnd v c c +15 v in 1 0v, 2.4 v v o +15 v 15 v gnd r l v+ v nc x talk isolation = 20 log c v s c v o 0v, 2.4 v 50 v s s 1 in 2 s 2 r g = 50 d 1 d 2 c = rf bypass figure 4. channel-to-channel crosstalk figure 5. charge injection c l 1000 pf v g 3 v d v+ v r g 15 v gnd in s v o +15 v v o v o in x on on off v o = measured voltage error due to charge injection the charge injection in coulombs is q = c l x v o
DG211B/212b vishay siliconix document number: 70040 s-00788erev. h, 24-apr-00 www.vishay.com faxback 408-970-5600 4-7 figure 6. sample-and-hold lm101a +15 v 15 v 30 pf +15 v 15 v v DG211B 50 pf 1000 pf j202 j500 j507 +15 v 2n4400 15 v v in v out 1 k 200 w 5 m 5.1 m aquisition time = 25 s aperature time = 1 s sample to hold offset = 5 mv droop rate = 5 mv/s logic input low = sample high = hold + v l v+ + 5 v f c1 f c2 ttl control 150 pf 1500 pf +15 v DG211B gnd 30 pf lm101a +15 v 15 v frequency hz 1 10 100 1 k 10 k 100 k 1 m 40 0 160 120 80 voltage gain db f c4 select f c3 select f c2 select f c1 select r 1 = 10 k r 2 = 10 k r 3 = 1 m v out v 1 v c 4 c 3 c 2 c 1 f l1 f c4 f l2 f l3 f l4 a l (voltage gain below break frequency) = = 100 (40 db) r 3 r 1 f c (break frequency) = 1 2 r 3 c x 1 2 r 1 c x f l (unity gain frequency) = max attenuation = r ds(on) 10 k 47 db 0.015 f 0.15 f figure 7. active low pass filter with digitally selected break frequency 15 v + f c3 40
DG211B/212b vishay siliconix www.vishay.com faxback 408-970-5600 4-8 document number: 70040 s-00788erev. h, 24-apr-00 figure 8. a precision amplifier with digitally programable input and gains gain = gain 1 (x1) gain 2 (x10) gain 3 (x100) gain 4 (x1000) 15 v +15 v 15 v gnd dg419 30 pf +15 v +15 v 15 v dg212b logic high = switch on + lm101a r f + r g r g v in1 v in2 ch r f1 18 k r f2 9.9 k r f3 100 k r g3 100 r g2 100 r g1 2 k v+ v gnd v +5 v v l

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